1. Field of the Invention
The invention relates to an exposure process in which a substrate is irradiated with UV light, in which outside the area in which a pattern is formed (area in which a semiconductor component (a circuit pattern or the like) is formed), alignment marks are formed, and to which a photoresist has been applied, and in which the photoresist which has been applied to the area provided with the alignment marks is thus exposed. The invention furthermore relates to a device for carrying out the process.
2. Description of Related Art
In the exposure of a mask pattern formed in a mask, such as a circuit or the like, onto a substrate (hereinafter called a “wafer”), the mask is positioned relative to the wafer to expose the mask pattern onto a given location of the wafer. For this positioning, the mask is provided with mask alignment marks and the workpiece is provided with workpiece alignment marks. The mask and the workpiece are moved such that the positional ratio of the two alignment marks becomes a given positional ratio (for example, agrees with a given positional ratio) and they are positioned relative to one another. The mask pattern is thus exposed onto the wafer and a pattern is formed on the wafer. Workpiece alignment marks (hereinafter called only “alignment marks”) are used for positioning of the mask to the workpiece, as was described above. Normally alignment marks are located outside the area in which a pattern, such as a circuit or the like, is formed.
Depending on the exposure device to be used, there are cases in which the alignment marks are located in the peripheral area of the region of the pattern to be formed in the wafer, as is shown, for example, in FIG. 10. In one such case, as is described below, films are placed in multiple layers on one another on the alignment marks AM, when the pattern is formed by a conventional process. As the process continues, the poorer the visual detectability of the alignment marks becomes and the more difficult it is to determine them.
The production of a pattern by the conventional process in the case of an arrangement of the alignment marks in the peripheral area of the wafer is described below in a simplified manner using FIGS. 11(a) to 11(n).
(1) First, alignment marks and an element pattern are formed on the wafer. To form the alignment marks and the element pattern on the wafer there is an exposure process, a development process and the like, which are however not described here.
Alignment marks AM are formed in the peripheral area of the wafer W by the above described process, as is shown in FIG. 11(a). FIG. 11(a) is a cross section in which the wafer W has been cut by a plane which is perpendicular to its surface. The top of the wafer W, as is shown below using FIG. 11(n), is provided, for example, with cross-shaped alignment marks AM (FIG. 11(a) is a cross section corresponding to line A—A as shown in FIG. 11(n)).
(2) As is shown in FIG. 11(b), on the wafer which is provided with the alignment marks AM and the element pattern, films such as oxide films (SiO2), nitride films (SiN) and the like are formed.
(3) As is shown in FIG. 11(c), a resist is applied.
(4) As is shown in FIG. 11(d), the mask pattern (element pattern) is exposed. Here, positioning of the mask relative to the workpiece is using the alignment marks AM on the wafer W and the mask alignment marks located in the mask. In FIG. 11(d), the exact arrangement of the element pattern is not shown.
As is shown in FIG. 11(e), the peripheral area is exposed.
(6) The resist is developed. For a positive resist, as is shown in FIG. 11(f), the exposed area is dissolved in a development solution.
(7) As is shown in FIG. 11(g), the films are etched, the resist being used as a mask. The films in the area in which there is no resist are removed.
(8) As is shown in FIG. 11(h) the resist is detached. In this way, the second pattern layer is formed.
(9) As is shown in FIGS. 11(i) to 11(k), layer formation (in FIG. 11(i) polysilicon (poly-Si)) is performed, the resist is applied and exposure carried out. Furthermore, as is shown in FIGS. 11(l) to 11(n), development, etching and removal are performed, and thus, the third pattern layer is formed. In this way, a second film layer and a third film layer are formed on the alignment marks AM which are formed in the peripheral area of the wafer, as is shown in FIG. 11(n).
In the above described process, a multilayer film is deposited on the alignment marks, the farther the process continues, as was described above. By absorption of light by the respective layer, and by refraction of the light on the boundary surface, in the positioning of the mask relative to the workpiece, the visual detectability of the alignment marks is degraded, by which determination gradually becomes difficult.
In order to prevent the above described disadvantage, in a conventional exposure device of the “step & repeat” type (stepper), in the peripheral area of the respective element pattern (in the gap between the respective element patterns within the region in which the pattern is formed), there are alignment marks. Upon each exposure of the pattern new alignment marks were exposed on the uppermost formed layer of the peripheral area (gap) of the respective element pattern.
However, in the case in which the alignment marks are located in the peripheral area of the wafer, as is shown in FIG. 10, the above described process cannot be used. As is shown in FIG. 11(n), a multilayer film is deposited on the alignment marks. The farther the process continues and the more layers are deposited, the more the visual detectability is degraded and the more difficult the determination of the alignment marks.
If, independently of a mask with a pattern, such as a fine circuit or the like, which is formed in the actual workpiece, a mask is used in which a pattern for exposure of the alignment marks is formed, and if in the manner shown in FIG. 10, the alignment marks located in the peripheral area of the wafer are exposed, the above described disadvantage can be eliminated. However, if a stepper is used for exposure only of the areas of the alignment marks, the production rate capacity for exposure of a fine circuit pattern, which is the actual purpose, is accordingly smaller.